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Integrated Circuit Systems, Inc.
ICS9248-192
Frequency Timing Generator for Transmeta Systems
Recommended Application: Transmeta Output Features: * 1CPU(2.5V or 3.3V selectable) up to 66.6MHz & overclocking of 66MHz. * * * * 6 PCI (3.3V) @ 33.3MHz (all are free running selectable). 1 REF (3.3V) at 14.318MHz. 1 48MHz (3.3V). 1 24_48MHz selectable output.
Pin Configuration
GNDREF X1 X2 PD# PCICLK0 PCICLK1 PCICLK2 GNDPCI VDDPCI PCICLK3 PCICLK4 PCICLK5 SDATA SCLK
1 2 3 4 5 6 7 8 9 10 11 12 13 14
Features: * Supports Spread Spectrum modulation for CPU and PCI clocks, default -0.4 downspread. * Efficient Power management scheme through stop clocks and power down modes. * Uses external 14.318MHz crystal, no external load cap required for CL=18pF crystal. * 28-pin TSSOP package, 4.40mm (173mil). Skew Characteristics: * CPU - CPU <175ps * PCI - PCI < 500ps * CPU(early) - PCI = 1.5ns - 4ns.
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VDDREF REF CPU_STOP# VDDLCPU GNDLCPU CPUCLK0 PCI_STOP# GND_Core VDD_Core SEL66/60# VDD48 GND48 48MHz/CPU3.3v_2.5V#sel 24-48MHz/Sel48_24#
28-Pin TSSOP
Block Diagram
PLL2 /2 X1 X2 XTAL OSC PLL1 Spread Spectrum 48MHz 24_48MHz
REF
CPU DIVDER
Stop
CPUCLK0
SEL48_24# CPU3.3V_2.5V#sel SEL66/60# PD# PCI_STOP# CPU_STOP# SDATA SCLK
Control Logic Config. Reg.
PCI DIVDER
Stop
6
PCICLK (5:0)
Power Groups
VDD_Core, GND_Core = PLL core VDDREF, GNDREF = REF, X1, X2 VDDPCI, GNDPCI = PCICLK (5:0) VDD48, GND48 = 48MHz (1:0)
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ICS9248-192
ICS9248-192
Pin Descriptions
Pin number 1 2 3 4 12, 11, 10, 7, 6, 5 8 9 15 13 14 16 48MHz 17 18 GND48 VDD48 Output Power Power Pin name GNDREF X1 X2 PD# PCICLK (5:0) GNDPCI VDDPCI Sel48_24# 24_48MHz SDATA SCLK CPU3.3-2.5# Type Power Input Output Input Output Power Power Input Output I/O IN Input Description Ground for 14.318 MHz reference clock outputs 14.318 MHz crystal input 14.318 MHz crystal output Asynchronous active low input pin used to power down the device into a low power state. The internal clocks are disabled and the VCO and the crystal are stopped. The latency of the power down will not be greater than 3ms. 3.3V PCI clock outputs, free running selectable Ground for PCI clock outputs 3.3V power for the PCI clock outputs Selects 24MHz (0) or 48MHz (1) output Selectable output either 24MHz or 48MHz Data pin for I2C circuitry 5V tolerant Clock pin of I2C circuitry 5V tolerant 3.3 (1) or 2.5 (0) VDD buffer strength selection, has pullup to VDD, nominal 30K resistor. 3.3V 48 MHz clock output, fixed frequency clock typically used with USB devices Ground for 48 MHz clocks 3.3V power for 48/24 MHz clocks Control for the frequency of clocks at the CPU & PCICLK output pins. "0" = 60 MHz. "1" = 66.6 MHz. The PCI clock is multiplexed to run at 33.3 MHz for both selected cases. Isolated 3.3V power for core Isolated ground for core Synchronous active low input used to stop the PCICLK in active low state. It will not effect PCICLK_F or any other outputs. CPU clock outputs selectable 2.5V or 3.3V. Ground for CPU clock outputs 2.5V or 3.3V power for CPU clock outputs Asynchronous active low input pin used to stop the CPUCLK in active low state, all other clocks will continue to run. The CPUCLK will have a "Turnon " latency of at least 3 CPU clocks. 3.3V 14.318 MHz reference clock output 3.3V power for 14.318 MHz reference clock outputs.
19
SEL 66/60#
Input
20 21 22 23 24 25 26 27 28
VDD_Core GND_Core PCI_Stop# CPUCLK0 GNDLCPU VDDLCPU CPU_STOP# REF VDDREF
Power Power Input Output Power Power Input Output Power
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ICS9248-192
CPU Select Functions
SEL 66/60# 0 1 CPU (MHz) 60MHz 66.6MHz
Power Management Clock Enable Configuration
C P U _ S TO P # X 0 0 1 1 P C I _ S TO P # X 0 1 0 1 P W R _ DW N # 0 1 1 1 1 CPUCLK L ow Low Low 60/66.6MHz 60/66.6MHz PCICLK L ow Low 33.3 MHz Low 33.3 MHz REF Stopped Running Running Running Running Cr ystal Off Running Running Running Running VCOs Off Running Running Running Running
Full clock cycle timing is guaranteed at all times after the system has initially powered up except where noted. During power up and power down operations using the PD# pin will not cause clocks of a short or longer pulse than that of the running clock. The first clock pulse coming out of a stopped clock condition may be slightly distorted due to clock network charging circuitry. Board routing and signal loading may have a large impact on the initial clock distortion also.
ICS9248-192 Power Management Requirements
SIGNAL CPU_ STOP# PCI_STOP# PD# SIGNAL STATE 0 ( D i s a bl e d ) 2 1 (Enabled)1 0 (Disabled)2 1 (Enabled)1 1 ( N o r m a l O p e ra t i o n ) 3 0 (Power Down)4 L a t e n cy No. of rising edg es of free running PCICLK 1 1 1 1 3ms 2max
Notes. 1. Clock on latency is defined from when the clock enable goes active to when the first valid clock comes out of the device. 2. Clock off latency is defined from when the clock enable goes inactive to when the last clock is driven low out of the device. 3. Power up latency is when PD# goes inactive (high) to when the first valid clocks are output by the device. 4. Power down has controlled clock counts applicable to CPUCLK, PCICLK only. The REF will be stopped independant of these.
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ICS9248-192
General I2C serial interface information
The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note.
How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 6 * ICS clock will acknowledge each byte one at a time. * Controller (host) sends a Stop bit
How to Write:
Controller (Host) Start Bit Address D2(H) Dummy Command Code ICS (Slave/Receiver)
How to Read:
* * * * * * * * Controller (host) will send start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 6 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit
* * * * * * * *
How to Read:
Controller (Host) Start Bit Address D3(H) ICS (Slave/Receiver)
ACK ACK
Dummy Byte Count
ACK Byte Count
ACK
ACK
Byte 0
Byte 0
ACK
Byte 1
ACK
Byte 1
ACK
Byte 2
ACK
Byte 2
ACK
Byte 3
ACK
Byte 3
ACK
Byte 4
ACK
Byte 4
ACK
Byte 5
ACK
Byte 5
ACK
Byte 6
ACK
Byte 6
ACK
Stop Bit
ACK Stop Bit
Notes:
1. 2. 3. 4. 5. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown.
6.
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ICS9248-192
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Bit Bit2 FS4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 2,7:4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit7 FS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 Bit6 FS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 Bit5 FS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 Bit4 FS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 CPU
60 60 60 60 66.6 66.6 66.6 66.6 67.32 68.64 69.96 72.6 61.5 63 64 65 60 66.6 50 48 58.8 57.6 56.4 54 60 60 60 60 66.6
PCI
30 30 30 30 33.3 33.3 33.3 33.3 33.66 34.32 34.98 36.3 30.75 31.5 32 32.5 30 33.3 25 24 29.4 28.8 28.2 27 30 30 30 30 33.3
Spread %
-0.4 % down spread -0.6 % down spread -0.8 % down spread -1.0 % down spread -0.4 % down spread -0.6 % down spread -0.8 % down spread -1.0 % down spread 2% over-clocking 4% over-clocking 6% over-clocking 10% over-clocking over-clocking over-clocking over-clocking over-clocking +/- 0.5% center spread +/- 0.5% center spread under-clocking under-clocking 2% under-clock 4% under-clock 6% under-clock 10% under-clock -1.4 % down spread -1.6 % down spread -1.8 % down spread -2.0 % down spread -1.4 % down spread
PWD
00000
Bit3 Bit1 Bit0
66.6 33.3 -1.6 % down spread 1 1 0 1 66.6 33.3 -1.8 % down spread 1 1 1 0 66.6 33.3 -2.0 % down spread 1 1 1 1 Hardware latch inputs can only access these frequencies 0-Frequency is seleced by hardware select. Latched input 1-Frequency is seleced by Bit 2, 7:4 0-Normal 1-Spread spectrun Enabled 0-Running 1-Tristate all outputs
0 0 0
Note: PWD = Power-Up Default
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ICS9248-192
Byte 1: PCI Stop
Byte 2: Stop Clocks
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN# 12 11 10 7 6 5 -
PWD 1 1 1 1 1 1 X X
DESCRIPTION PCICLK5 PCICLK4 PCICLK3 PCICLK2 PCICLK1 PCICLK0 R e s e r ve d Reserved
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN# 16 15 23 27 -
PWD 1 1 1 1 X X X X
DESCRIPTION 48MHz 48_24MHz CPUCLK0 REF R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d
Note: 1 = Inactive 0 = Active Byte 3:Free-Running Enable
Note: 1 = Inactive 0 = Active Byte 4: Reserved
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN# 12 11 10 7 6 5 -
PWD 1 1 1 1 1 1 X X
DESCRIPTION PCICLK5 PCICLK4 PCICLK3 PCICLK2 PCICLK1 PCICLK0 R e s e r ve d R e s e r ve d
BIT PIN# PWD Bit 7 X Bit 6 X Bit 5 X Bit 4 X Bit 3 X Bit 2 X Bit 1 X Bit 0 X
DESCRIPTION R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d
Note: 0 = Not free-running (controlled by PCI_STOP# pin) 1 = Free-running (can override Byte1 PCI Stop Control) Byte 5: Reserved Byte 6: Reserved
BIT PIN# PWD Bit 7 X Bit 6 X Bit 5 X Bit 4 X Bit 3 X Bit 2 X Bit 1 X Bit 0 X
DESCRIPTION R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d
BIT PIN# PWD Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 1 Bit 1 1 Bit 0 0
DESCRIPTION R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d
Note: PWD = Power-Up Default
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ICS9248-192
CPU_STOP# Timing Diagram
CPUSTOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPUCLKs for low power operation. CPU_STOP# is synchronized by the ICS9248-192. The minimum that the CPUCLK is enabled (CPU_STOP# high pulse) is 100 CPUCLKs. All other clocks will continue to run while the CPUCLKs are disabled. The CPUCLKs will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPUCLK on latency is less than 4 CPUCLKs and CPUCLK off latency is less than 4 CPUCLKs.
INTERNAL CPUCLK PCICLK CPU_STOP# PCI_STOP# (High) PD# (High) CPUCLK
Notes: 1. All timing is referenced to the internal CPUCLK. 2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized to the CPUCLKs inside the ICS9248-192. 3. All other clocks continue to run undisturbed. 4. PD# and PCI_STOP# are shown in a high (true) state.
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9248-192. It is used to turn off the PCICLK clocks for low power operation. PCI_STOP# is synchronized by the ICS9248-192 internally. The minimum that the PCICLK clocks are enabled (PCI_STOP# high pulse) is at least 10 PCICLK clocks. PCICLK clocks are stopped in a low state and started with a full high pulse width guaranteed. PCICLK clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.
Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248-192 device.) 2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized inside the ICS9248-192. 3. All other clocks continue to run undisturbed. 4. PD# and CPU_STOP# are shown in a high (true) state.
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ICS9248-192
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is an asynchronous active low input. This signal is synchronized internally by the ICS9248-192 prior to its control action of powering down the clock synthesizer. Internal clocks will not be running after the device is put in power down state. When PD# is active (low) all clocks are driven to a low state and held prior to turning off the VCOs and the crystal oscillator. The power on latency is guaranteed to be less than 3ms. The power down latency is less than three CPUCLK cycles. PCI_STOP# and CPU_STOP# are don't care signals during the power down operations.
CPUCLK (Internal) PCICLK (Internal) PD#
CPUCLK PCICLK_F, PCICLK
REF INTERNAL VCOs INTERNAL CRYSTAL OSC.
Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device). 2. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside the ICS9248. 3. The shaded sections on the VCO and the Crystal signals indicate an active clock is being generated.
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ICS9248-192
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . 0C to +70C Storage Temperature . . . . . . . . . . . . . . . . . . . -65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage V DDL = 2.5V, VDD = 3.3 V +/-5% (unless otherwise stated) PARAMETER Input High Voltage Input Low Voltage Input High Current Input Low Current Input Low Current Operating Supply Current Power Down Supply Current Input frequency Input Capacitance1 Transition Time1 Clk Stabilization1 Skew1
1
SYMBOL V IH VIL I IH I IL1 I IL2 I DD2.5OP66 I DD3.3OP66 I DD3.3PD Fi CIN CINX Ttrans TSTAB TCPU-PCI
CONDITIONS
MIN 2 V SS - 0.3 -5 -200
TYP
VIN = VDD VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with pull-up resistors CL = 0 pF; Select @ 66.6MHz CL = 0 pF; Select @ 66.6MHz CL = 0 pF; With input address to Vdd or GND VDD = 3.3 V; Logic Inputs X1 & X2 pins To 1st crossing of target Freq. From VDD = 3.3 V to 1% target Freq. VT = 1.5 V; VTL = 1.25 V
MAX UNITS VDD + 0.3 V 0.8 V 5 mA mA mA 15 mA 80 mA A 600 16 5 45 3 3 MHz pF pF ms ms ns
11 27
14.318
1.5
4
Guaranteed by design, not 100% tested in production.
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ICS9248-192
Electrical Characteristics - CPUCLK
TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter
1
SYMBOL VOH2B VOL2B I OH2B IOL2B tr2B tf2B
1 1
CONDITIONS IOH = -12.0 mA IOL = 12 mA VOH = 1.7 V VOL = 0.7 V VOL = 0.4 V, VOH = 2.0 V VOH = 2.0 V, V OL = 0.4 V VT = 1.25 V VT = 1.25 V
MIN 1.8
TYP
27 0.4 0.4 44
MAX UNITS V 0.4 V -27 mA mA 1.6 1.6 55 175 250 ns ns % ps ps ps
dt2B1 tsk2B1
tjcyc-cyc2B1 VT = 1.25 V tjabs2B1 VT = 1.25 V
-250
+250
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - REF
TA = 0 - 70C; VDD = 3.3 V , VDDL = 2.5V, +/-5%; CL = 10 - 20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time1 Fall Time1 Duty Cycle1 Jitter1 Jitter1 SYMBOL VOH5 VOL5 I OH5 IOL5 tr5 tf5 dt5 tjcyc-cyc5 tjabs5 tjcyc-cyc5 tjabs5 CONDITIONS IOH = -12 mA IOL = 9 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, V OL = 0.4 V VT = VT = VT = VT = VT = 1.5 V 1.5 V, 1.5 V, 1.5 V, 1.5 V, 45 REF REF 48 MHz 48 MHz MIN 2.6 TYP MAX UNITS V 0.4 V -22 mA mA 4 4 55 1000 800 500 800 ns ns % ps ps ps ps
16
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ICS9248-192
Electrical Characteristics - 48MHz
TA = 0 - 70C; VDD = 3.3 V , VDDL = 2.5V, +/-5%; CL = 10 - 20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time1 Fall Time
1 1
SYMBOL VOH5 VOL5 I OH5 IOL5 tr5 tf5 dt5 tjcyc-cyc5 tjabs5 tjcyc-cyc5 tjabs5
CONDITIONS IOH = -12 mA IOL = 9 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, V OL = 0.4 V VT = VT = VT = VT = VT = 1.5 V 1.5 V, 1.5 V, 1.5 V, 1.5 V,
MIN 2.6
TYP
16
MAX UNITS V 0.4 V -22 mA mA 1.2 1.2 ns ns % ps ps ps ps
Duty Cycle Jitter1 Jitter1
45 REF REF 48 MHz 48 MHz
55 1000 800 500 800
Electrical Characteristics - PCICLK
TA = 0 - 70C; VDD = 3.3 V, VDDL = 2.5V +/-5%; CL = 30 pF PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time1 Fall Time Skew
1 1
SYMBOL VOH1 VOL1 IOH1 IOL1 tr1 tf1 dt1 tsk1 tjcyc-cyc tjabs1
1
CONDITIONS IOH = -18 mA IOL = 9.4 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, V OL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
MIN 2.1
TYP
16
MAX UNITS V 0.4 V -22 mA 57 mA 2 2 ns ns % ps ps ps
Duty Cycle1
45
55 500 500 500
Jitter
1
Guaranteed by design, not 100% tested in production.
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ICS9248-192
N
c
SYMBOL
In Millimeters In Inches COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX 1.20 0.15 1.05 0.30 MIN .002 .032 .007 MAX .047 .006 .041 .012 0.05 0.80 0.19
L
A A1 A2 b c D E
INDEX AREA
E1
E
0.09 0.20 SEE VARIATIONS 6.40 BASIC 4.30 4.50 0.65 BASIC 0.45 0.75 SEE VARIATIONS 0 8 0.10
.0035 .008 SEE VARIATIONS 0.252 BASIC .169 .177 0.0256 BASIC .018 .030 SEE VARIATIONS 0 8 .004
12 D
E1 e L N
A2 A1
A
aaa VARIATIONS
-C-
N 28
D mm. MIN 9.60 MAX 9.80 MIN .378
D (inch) MAX .386
7/6/00 Rev C
e
b
SEATING PLANE
aaa C
MO-153 JEDEC Doc.# 10-0035
4.40 mm. Body, 0.65 mm. pitch TSSOP (0.0256 Inch) (173 mil)
Ordering Information
ICS9248yG-192-T
Example:
ICS XXXX y G - PPP - T
Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type G = TSSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device
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